Category: JEDEC

Showing 46–60 of 419 results

  • JEDEC JEP145

    $31.80

    GUIDELINE FOR ASSESSING THE CURRENT-CARRYING CAPABILITY OF THE LEADS IN A POWER PACKAGE SYSTEM

    Published by Publication Date Number of Pages
    JEDEC 02/01/2003 11
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  • JEDEC JEP146A

    $36.00

    GUIDELINES FOR SUPPLIER PERFORMANCE RATING

    Published by Publication Date Number of Pages
    JEDEC 01/01/2009 20
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  • JEDEC JEP147

    $31.80

    PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)

    Published by Publication Date Number of Pages
    JEDEC 10/01/2003 11
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  • JEDEC JEP148B

    $46.80

    RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES BASED ON PHYSICS OF FAILURE RISK AND OPPORTUNITY ASSESSMENT

    Published by Publication Date Number of Pages
    JEDEC 01/01/2014 38
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  • JEDEC JEP149

    $35.40

    APPLICATION THERMAL DERATING METHODOLOGIES

    Published by Publication Date Number of Pages
    JEDEC 11/01/2004 17
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  • JEDEC JEP150.01

    $40.20

    STRESS-TEST-DRIVEN QUALIFICATION OF AND FAILURE MECHANISMS ASSOCIATED WITH ASSEMBLED SOLID STATE SURFACE-MOUNT COMPONENTS

    Published by Publication Date Number of Pages
    JEDEC 06/01/2013 24
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  • JEDEC JEP151

    $37.20

    , Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices

    Published by Publication Date Number of Pages
    JEDEC 12/01/2015 24
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  • JEDEC JEP152

    $43.20

    DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD

    Published by Publication Date Number of Pages
    JEDEC 05/01/2007 29
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  • JEDEC JEP153A

    $36.00

    CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPURATURES

    Published by Publication Date Number of Pages
    JEDEC 03/01/2014 20
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  • JEDEC JEP154

    $45.60

    GUIDELINE FOR CHARACTERIZING SOLDER BUMP ELECTROMIGRATION UNDER CONSTANT CURRENT AND TEMPERATURE STRESS

    Published by Publication Date Number of Pages
    JEDEC 01/01/2008 34
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  • JEDEC JEP155B

    $54.60

    RECOMMENDED ESD TARGET LEVELS FOR HBM QUALIFICATION

    Published by Publication Date Number of Pages
    JEDEC 07/01/2018 58
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  • JEDEC JEP156A

    $40.20

    CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

    Published by Publication Date Number of Pages
    JEDEC 03/01/2018 24
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  • JEDEC JEP157A

    $124.80

    Recommended ESD-CDM Target Levels

    Published by Publication Date Number of Pages
    JEDEC 04/01/2022 174
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  • JEDEC JEP158

    $37.20

    3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions

    Published by Publication Date Number of Pages
    JEDEC 11/01/2009 23
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  • JEDEC JEP159A

    $44.40

    PROCEDURE FOR THE EVQLUQTION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY

    Published by Publication Date Number of Pages
    JEDEC 07/01/2015 30
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