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Category: JEDEC
Showing 346–360 of 419 results
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JEDEC JESD8-22B
$46.80Add to cartHSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODT
Published by Publication Date Number of Pages JEDEC 04/01/2014 38 -
JEDEC JESD8-23
$30.60Add to cartUNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS
Published by Publication Date Number of Pages JEDEC 10/01/2009 9 -
JEDEC JESD8-24
$33.60Add to cartPOD12-1.2 V Pseudo Open Drain Interface
Published by Publication Date Number of Pages JEDEC 08/01/2011 16 -
JEDEC JESD8-25
$33.60Add to cartPOD10 – 1.0 V Pseudo Open Drain Interface
Published by Publication Date Number of Pages JEDEC 09/01/2011 16 -
JEDEC JESD8-26
$28.80Add to cart1.2 V High-Speed LVCMOS (HS_LVCMOS) Interface
Published by Publication Date Number of Pages JEDEC 09/01/2011 8 -
JEDEC JESD8-28
$30.60Add to cart300 mV INTERFACE
Published by Publication Date Number of Pages JEDEC 06/01/2015 10 -
JEDEC JESD8-29
$32.40Add to cart0.6 V Low Voltage Swing Terminated Logic (LVSTL06)
Published by Publication Date Number of Pages JEDEC 12/01/2016 14 -
JEDEC JESD8-30A
$36.00Add to cartPOD125 – 1.25 V Pseudo Open Drain I/O
Published by Publication Date Number of Pages JEDEC 06/01/2019 20 -
JEDEC JESD8-31
$28.80Add to cart1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE
Published by Publication Date Number of Pages JEDEC 03/01/2018 8 -
JEDEC JESD8-3A
$30.60Add to cartADDENDUM No. 3A to JESD8 – GUNNING TRANSCEIVER LOGIC (GTL) LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
Published by Publication Date Number of Pages JEDEC 05/01/2007 9 -
JEDEC JESD8-4
$28.80Add to cartADDENDUM No. 4 to JESD8 – CENTER-TAP-TERMINATED (CTT) INTERFACE LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
Published by Publication Date Number of Pages JEDEC 11/01/1993 8 -
JEDEC JESD8-5A.01
$32.40Add to cartADDENDUM No. 5 to JESD8 – 2.5 V 0.2 V (NORMAL RANGE), AND 1.8 V TO 2.7 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT
Published by Publication Date Number of Pages JEDEC 09/01/2007 13 -
JEDEC JESD8-6
$36.00Add to cartADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
Published by Publication Date Number of Pages JEDEC 08/01/1995 20 -
JEDEC JESD8-7A
$32.40Add to cartADDENDUM No. 7 to JESD8 – 1.8 V + -0.15 V (NORMAL RANGE), AND 1.2 V – 1.95 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT
Published by Publication Date Number of Pages JEDEC 06/01/2006 13 -
JEDEC JESD8-8
$35.40Add to cartADDENDUM No. 8 to JESD8 – STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
Published by Publication Date Number of Pages JEDEC 08/01/1996 18
