Category
JEDEC JESD 36
$56.00 $33.60
STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES
Published by | Publication Date | Number of Pages |
JEDEC | 06/01/1996 | 15 |
JEDEC JESD 36 – STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES
This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device’s power supply. More specifically this standardizes 5 V – tolerant logic prducts that run from ‘low voltage’ (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses.
Product Details
- Published:
- 06/01/1996
- Number of Pages:
- 15
- File Size:
- 1 file , 43 KB
- Note:
- This product is unavailable in Russia, Ukraine, Belarus
Related products
-
JEDEC JESD92
$74.00$44.40Add to cartPROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS
Published by Publication Date Number of Pages JEDEC 08/01/2003 32 -
JEDEC JESD96A
$106.00$63.60Add to cartRADIO FRONT END – BASEBAND (RF-BB) INTERFACE
Published by Publication Date Number of Pages JEDEC 02/01/2006 61 -
JEDEC J-STD-033D
$79.00$47.40Add to cartHandling, Packing, Shipping and Use of Moisture, Reflow, and Process Sensitive Devices
Published by Publication Date Number of Pages JEDEC 04/01/2018 31 -
JEDEC JESD9C
$141.00$84.60Add to cartInspection Criteria for Microelectronic Packages and Covers
Published by Publication Date Number of Pages JEDEC 05/01/2017 82